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sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 sn65mlvd20xx multipoint-lvds line driver and receiver 1 features 2 applications 1 ? low-voltage differential 30- ? to 55- ? line drivers ? low-power, high-speed, short-reach alternative and receivers for signaling rates (1) up to to tia/eia-485 100 mbps, clock frequencies up to 50 mhz ? backplane or cabled multipoint data and clock ? type-1 receivers incorporate 25 mv of transmission hysteresis (sn65mlvd200a, sn65mlvd202a) ? cellular base stations ? type-2 receivers provide an offset (100 mv) ? central office switches threshold to detect open-circuit and idle-bus ? network switches and routers conditions (sn65mlvd204a, sn65mlvd205a) ? meets or exceeds the m-lvds standard 3 description tia/eia-899 for multipoint data interchange the sn65mlvd20xx devices are multipoint low- ? controlled driver output voltage transition times voltage differential (m-lvds) line drivers and receivers that are optimized to operate at signaling for improved signal quality rates up to 100 mbps. all parts comply with the ? ? 1 v to 3.4 v of common-mode voltage range multipoint low-voltage differential signaling (m-lvds) allows data transfer with 2 v of ground noise standard tia/eia-899. ? bus pins high impedance when disabled the sn65mlvd20xx devices have enhancements or v cc 1.5 v over their predecessors. improved features include ? 200-mbps devices available (sn65mlvd201, controlled slew rate on the driver output to help sn65mlvd203, sn65mlvd206, sn65mlvd207) minimize reflections from unterminated stubs, which ? bus pin esd protection exceeds 8 kv results in better signal integrity. additionally, 8-kv esd protection on the bus pins for more robustness. ? packages available: the same footprint definition was maintained making ? 8-pin soic for an easy drop-in replacement for a system sn65mlvd200a, sn65mlvd204a performance upgrade. ? 14-pin soic the devices are characterized for operation from sn65mlvd202a, sn65mlvd205a ? 40 c to 85 c. ? improved alternatives to the sn65mlvd200, sn65mlvd202a, sn65mlvd204a, and device information (1) sn65mlvd205a devices part number package body size (nom) (1) the signaling rate of a line, is the number of voltage sn65mlvd200a soic (8) 4.90 mm 3.91 mm transitions that are made per second expressed in the units sn65mlvd204a bps (bits per second). sn65mlvd202a soic (14) 8.65 mm 3.91 mm sn65mlvd205a (1) for all available packages, see the orderable addendum at the end of the data sheet. logic diagrams (positive logic) 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. 4 31 2 de d re r 67 ab 54 2 3 de d re r 12 11 ab 10 9 yz sn65mlvd202a, sn65mlvd205a sn65mlvd200a, sn65mlvd204a productfolder sample &buy technical documents tools & software support &community
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com table of contents 9.1 overview ................................................................. 16 1 features .................................................................. 1 9.2 functional block diagram ....................................... 16 2 applications ........................................................... 1 9.3 feature description ................................................. 16 3 description ............................................................. 1 9.4 device functional modes ........................................ 17 4 revision history ..................................................... 2 10 application and implementation ........................ 19 5 device comparison table ..................................... 3 10.1 application information .......................................... 19 6 pin configuration and functions ......................... 3 10.2 typical application ............................................... 19 7 specifications ......................................................... 4 11 power supply recommendations ..................... 23 7.1 absolute maximum ratings ...................................... 4 12 layout ................................................................... 23 7.2 esd ratings ............................................................ 4 12.1 layout guidelines ................................................. 23 7.3 recommended operating conditions ....................... 4 12.2 layout example .................................................... 27 7.4 thermal information .................................................. 4 13 device and documentation support ................. 28 7.5 electrical characteristics ........................................... 5 13.1 documentation support ........................................ 28 7.6 electrical characteristics ? driver ............................. 5 13.2 related links ........................................................ 28 7.7 electrical characteristics ? receiver ........................ 6 13.3 community resources .......................................... 29 7.8 electrical characteristics ? bus input and output ... 6 13.4 trademarks ........................................................... 29 7.9 switching characteristics ? driver ............................ 7 13.5 electrostatic discharge caution ............................ 29 7.10 switching characteristics ? receiver ...................... 7 13.6 glossary ................................................................ 29 7.11 typical characteristics ............................................ 8 14 mechanical, packaging, and orderable 8 parameter measurement information ................ 10 information ........................................................... 29 9 detailed description ............................................ 16 4 revision history changes from revision c (september 2015) to revision d page ? deleted features list item " meets 8-kv iec 61000-4-2, contact discharge " ...................................................................... 1 changes from revision b (june 2015) to revision c page ? deleted row " open circuit " from table 3 and table 4 as redundant .................................................................................. 17 ? changed from " v id 50 mv " to " v id 150 mv " in table 4 ............................................................................................... 17 ? changed from " ? 50 mv < v id < 150 mv " to " 50 mv < v id < 150 mv " in table 4 ................................................................ 17 changes from revision a (december 2003) to revision b page ? pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ..................................... 1 ? removed sn65mlvd204b from the data sheet .................................................................................................................... 1 ? changed ordering information to device comparison table ................................................................................................ 3 ? deleted |v id | min value in recommended operating conditions .......................................................................................... 4 ? changed multipoint configuration image ............................................................................................................................. 19 changes from original (december 2003) to revision a page ? deleted duplicate note from figure 23 ................................................................................................................................ 14 2 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 5 device comparison table part number footprint receiver type sn65mlvd200ad sn75176 type 1 sm65mlvd202ad sn75als180 type 1 sn65mlvd204ad sn75176 type 2 sm65mlvd205ad sn75als180 type 2 6 pin configuration and functions d package d package 8-pin soic 14-pin soic top view top view pin functions pin type description name soic-8 soic-14 a 6 12 i/o differential i/o b 7 11 i/o differential i/o d 4 5 i driver input de 3 4 i driver enable pin: high = enable, low = disable gnd 5 6, 7 power supply ground nc ? 1, 8 nc no internal connection r 1 2 o receiver output re 2 3 i receiver enable pin: high = disable, low = enable v cc 8 13, 14 power power supply, 3.3 v y ? 9 i/o differential i/o z ? 10 i/o differential i/o copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 12 3 4 5 6 7 1413 12 11 10 98 nc r re de d gndgnd v cc v cc ab z y nc 12 3 4 87 6 5 r re de d v cc ba gnd
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) min max unit supply voltage (2) , v cc ? 0.5 4 v d, de, re ? 0.5 4 v input voltage a, b (sn65mlvd200a and sn65mlvd204a) ? 1.8 4 v a, b (sn65mlvd202a, sn65mlvd205a) ? 4 6 v r ? 0.3 4 v output voltage range y, z, a, or b ? 1.8 4 v continuous power dissipation see thermal information storage temperature, t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. 7.2 esd ratings value unit all pins except a, b, y, 4000 human body model (hbm), per and z ansi/esda/jedec js-001, all pins (1) v (esd) electrostatic discharge a, b, y, and z 8000 v charged device model (cdm), per jedec all pins 1500 specification jesd22-c101, all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions min nom max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 v cc v v il low-level input voltage gnd 0.8 v voltage at any bus terminal v a v b v y or v z ? 1.4 3.8 v |v id | magnitude of differential input voltage v cc v r l differential load resistance 30 50 ? 1/t ui signaling rate 100 mbps t a operating free-air temperature ? 40 85 c 7.4 thermal information sn65mlvd200a, sn65mlvd202a, sn65mlvd204a sn65mlvd205a thermal metric (1) unit d (soic) d (soic) 8 pins 14 pins r ja junction-to-ambient thermal resistance 103.9 78.9 c/w r jc(top) junction-to-case (top) thermal resistance 50.6 39 c/w r jb junction-to-board thermal resistance 44.5 33.3 c/w jt junction-to-top characterization parameter 8.1 7.2 c/w jb junction-to-board characterization parameter 43.9 33 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report (spra953 ). 4 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 7.5 electrical characteristics over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit driver only re and de at v cc , r l = 50 ? , all others open 13 22 both disabled re at v cc , de at 0 v, r l = no load, all others open 1 4 i cc supply current ma both enabled re at 0 v, de at v cc , r l = 50 ? , all others open 16 24 receiver only re at 0 v, de at 0 v, all others open 4 13 r l = 50 ? , input to d is a 50-mhz 50% duty cycle square p d device power dissipation wave, 94 mw de = high, re = low, t a = 85 c (1) all typical values are at 25 c and with a 3.3-v supply voltage. 7.6 electrical characteristics ? driver over recommended operating conditions unless otherwise noted parameter test conditions min (1) typ (2) max unit |v ab | or differential output voltage magnitude 480 650 mv |v yz | see figure 14 |v ab | or change in differential output voltage magnitude ? 50 50 mv |v yz | between logic states v os(ss) steady-state common-mode output voltage 0.8 1.2 v change in steady-state common-mode output v os(ss) see figure 15 ? 50 50 mv voltage between logic states v os(pp) peak-to-peak common-mode output voltage 150 mv v y(oc) or maximum steady-state open-circuit output voltage 0 2.4 v v a(oc) see figure 19 v z(oc) or maximum steady-state open-circuit output voltage 0 2.4 v v b(oc) v p(h) voltage overshoot, low-to-high level output 1.2 v ss v see figure 17 v p(l) voltage overshoot, high-to-low level output ? 0.2 v ss v i ih high-level input current (d, de) v ih = 2 v to v cc 0 10 a i il low-level input current (d, de) v il = gnd to 0.8 v 0 10 a |i os | differential short-circuit output current magnitude see figure 4 24 ma ? 1.4 v (v y or v z ) 3.8 v, i oz high-impedance state output current (driver only) ? 15 10 a other output = 1.2 v ? 1.4 v (v y or v z ) 3.8 v, other i o(off) power-off output current ? 10 10 a output = 1.2 v, 0 v v cc 1.5 v v i = 0.4 sin(30e6 t) + 0.5 v, (3) c y or c z output capacitance other input at 1.2 v, driver 3 pf disabled v ab = 0.4 sin(30e6 t) v, (3) c yz differential output capacitance 2.5 pf driver disabled c y/z output capacitance balance, (c y /c z ) 0.99 1.01 (1) the algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) all typical values are at 25 c and with a 3.3-v supply voltage. (3) hp4194a impedance analyzer (or equivalent) copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 7.7 electrical characteristics ? receiver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit type 1 50 v it+ positive-going differential input voltage threshold mv type 2 150 type 1 ? 50 see figure 9 , table 1 , and v it- negative-going differential input voltage threshold mv table 2 type 2 50 type 1 25 v hys differential input voltage hysteresis, (v it+ ? v it ? ) mv type 2 0 v oh high-level output voltage (r) i oh = ? 8 ma 2.4 v v ol low-level output voltage (r) i ol = 8 ma 0.4 v i ih high-level input current ( re) v ih = 2 v to v cc ? 10 0 a i il low-level input current ( re) v il = gnd to 0.8 v ? 10 0 a i oz high-impedance output current (r) v o = 0 v or 3.6 v ? 10 15 a c a or v i = 0.4 sin(30e6 t) + 0.5 v (2) , input capacitance 3 pf c b other input at 1.2 v c ab differential input capacitance v ab = 0.4 sin(30e6 t) v (2) 2.5 pf c a/b input capacitance balance, (c a/ c b ) 0.99 1.01 (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) hp4194a impedance analyzer (or equivalent) 7.8 electrical characteristics ? bus input and output over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit v a = 3.8 v, v b = 1.2 v, 0 32 receiver or transceiver with driver disabled i a v a = 0 v or 2.4 v, v b = 1.2 v ? 20 20 a input current v a = ? 1.4 v, v b = 1.2 v ? 32 0 v b = 3.8 v, v a = 1.2 v 0 32 receiver or transceiver with driver disabled i b v b = 0 v or 2.4 v, v a = 1.2 v ? 20 20 a input current v b = ? 1.4 v, v a = 1.2 v ? 32 0 receiver or transceiver with driver disabled i ab v a = v b, 1.4 v a 3.8 v ? 4 4 a differential input current (i a ? i b ) v a = 3.8 v, v b = 1.2 v, 0 v v cc 1.5 v 0 32 i a(off) receiver or transceiver power-off input current v a = 0 v or 2.4 v, v b = 1.2 v, 0 v v cc 1.5 v ? 20 20 a v a = ? 1.4 v, v b = 1.2 v, 0 v v cc 1.5 v ? 32 0 v b = 3.8 v, v a = 1.2 v, 0 v v cc 1.5 v 0 32 i b(off) receiver or transceiver power-off input current v b = 0 v or 2.4 v, v a = 1.2 v, 0 v v cc 1.5 v ? 20 20 a v b = ? 1.4 v, v a = 1.2 v, 0 v v cc 1.5 v ? 32 0 receiver input or transceiver power-off i ab(off) v a = v b , 0 v v cc 1.5 v, ? 1.4 v a 3.8 v ? 4 4 a differential input current (i a ? i b ) transceiver with driver disabled input c a v a = 0.4 sin (30e6 t) + 0.5 v (2) , v b = 1.2 v 5 pf capacitance transceiver with driver disabled input c b v b = 0.4 sin (30e6 t) + 0.5 v (2) , v a = 1.2 v 5 pf capacitance transceiver with driver disabled differential c ab v ab = 0.4 sin (30e6 t)v (2) 3 pf input capacitance transceiver with driver disabled input c a/b 0.99 1.01 capacitance balance, (c a /c b ) (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) hp4194a impedance analyzer (or equivalent) 6 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 7.9 switching characteristics ? driver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output 2 2.5 3.5 ns t phl propagation delay time, high-to-low-level output 2 2.5 3.5 ns t r differential output signal rise time see figure 17 2 2.6 3.2 ns t f differential output signal fall time 2 2.6 3.2 ns t sk(p) pulse skew (|t phl ? t plh |) 30 150 ps t sk(pp) part-to-part skew (2) 0.9 ns t jit(per) period jitter, rms (1 standard deviation) (3) 50-mhz clock input (4) 2 3 ps t jit(pp) peak-to-peak jitter (3) (5) 100 mbps 2 15 ? 1 prbs input (6) 55 150 ps t phz disable time, high-level-to-high-impedance output 4 7 ns t plz disable time, low-level-to-high-impedance output 4 7 ns see figure 18 t pzh enable time, high-impedance-to-high-level output 4 7 ns t pzl enable time, high-impedance-to-low-level output 4 7 ns (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same v/t conditions. (3) jitter is ensured by design and characterization. stimulus jitter has been subtracted from the numbers. (4) t r = t f = 0.5 ns (10% to 90%), measured over 30k samples. (5) peak-to-peak jitter includes jitter due to pulse skew (t sk(p) ). (6) t r = t f = 0.5 ns (10% to 90%), measured over 100k samples. 7.10 switching characteristics ? receiver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output 2 3.6 6 ns t phl propagation delay time, high-to-low-level output 2 3.6 6 ns t r output signal rise time 1 2.3 ns t f output signal fall time c l = 15 pf, see figure 22 1 2.3 ns type 1 100 300 ps t sk(p) pulse skew (|t phl ? t plh |) type 2 300 500 ps t sk(pp) part-to-part skew (2) 1 ns t jit(per) period jitter, rms (1 standard deviation) (3) 50-mhz clock input (4) 4 7 ps type 1 200 700 ps t jit(pp) peak-to-peak jitter (3) (5) 100 mbps 2 15 ? 1 prbs input (6) type 2 225 800 ps t phz disable time, high-level-to-high-impedance output 6 10 ns t plz disable time, low-level-to-high-impedance output 6 10 ns see figure 23 t pzh enable time, high-impedance-to-high-level output 10 15 ns t pzl enable time, high-impedance-to-low-level output 10 15 ns (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same v/t conditions. (3) jitter is ensured by design and characterization. stimulus jitter has been subtracted from the numbers. (4) v id = 200 mv pp (mlvd200a, 202a), v id = 400 mv pp (mlvd204a, 205a), v cm = 1 v, t r = t f = 0.5 ns (10% to 90%), measured over 30k samples. (5) peak-to-peak jitter includes jitter due to pulse skew (t sk(p) ) (6) v id = 200 mv pp (mlvd200a, 202a), v id = 400 mv pp (mlvd204a, 205a), v cm = 1 v, t r = t f = 0.5 ns (10% to 90%), measured over 100k samples. copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 7.11 typical characteristics figure 1. supply current vs frequency figure 2. supply current vs free-air temperature figure 4. receiver high-level output current figure 3. receiver low-level output current vs high-level output voltage vs low-level output voltage figure 6. receiver propagation delay figure 5. driver propagation delay vs free-air temperature vs free-air temperature 8 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 0 30 40 50 60 70 0 1 2 4 ? receiver low level output current ? ma v ol ? low level output voltage ? v 3 i ol 10 20 v cc = 3.6 v v cc = 3.3 v v cc = 3.0 v t a = 25c ?90 ?60 ?50 ?40 ?30 ?20 0 1 2 4 ? receiver high level output current ? ma v oh ? high level output voltage ? v 3 i oh ?80 ?70 v cc = 3.0 v ?10 0 v cc = 3.6 v v cc = 3.3 v t a = 25c 0 5 10 15 20 10 20 30 40 50 i f ? frequency ? mhz ? supply current ? ma cc tx rx v cc = 3.3 v v id = 200 mv v ic = 1 v t a = 25c 0 5 10 15 20 25 30 ?40 ?15 10 35 60 85 i ? supply current ? ma cc t a ? free-air temperature ? c v cc = 3.3 v f = 50 mhz v id = 200 mv v ic = 1 v rx tx 2 2.2 2.4 2.6 2.8 ?40 ?15 10 35 60 85 driver propagation delay ? ns t a ? free-air temperature ? c v cc = 3.3 v f = 1 mhz r l = 50 t phl t plh 3 3.20 3.40 3.60 3.80 4 ?40 ?15 10 35 60 85 receiver propagation delay ? ns t a ? free-air temperature ? c v cc = 3.3 v v id = 200 mv v ic = 1 v f = 1 mhz c l = 15 pf t plh t phl
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 typical characteristics (continued) figure 8. added driver peak-to-peak jitter vs signaling rate figure 7. added driver cycle-to-cycle jitter vs clock frequency figure 10. added receiver cycle-to-cycle jitter figure 9. added driver peak-to-peak jitter vs clock frequency vs free-air temperature figure 11. added receiver peak-to-peak jitter figure 12. added receiver peak-to-peak jitter vs signaling rate vs free-air temperature copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 0 60 120 180 240 300 ?40 ?15 10 35 60 85 t a ? free-air temperature ? c added receiver peak-to-peak jitter ? ps type-2 v id = 400 mv type-1 v id = 200 mv v cc = 3.3 v v ic = 1 v 2 15 -1 prbs nrz 0 60 120 180 240 300 20 40 60 80 100 added receiver peak-to-peak jitter ? ps signaling rate ? mbps type-2 v id = 400 mv type-1 v id = 200 mv v cc = 3.3 v t a = 25 c v ic = 1 v 2 15 -1 prbs nrz 40 48 56 64 72 80 ?40 ?15 10 35 60 85 added driver peak-to-peak jitter ? ps t a ? free-air temperature ? c v cc = 3.3 v v ic = 1 v f = 100 mbps 2 15 -1 prbs nrz 10 16 22 28 34 40 10 20 30 40 50 clock frequency ? mhz added receiver cycle-to-cycle jitter ? ps v cc = 3.3 v t a = 25c v ic = 1 v type-1 v id = 200 mv type-2 v id = 400 mv 0 6 12 18 24 30 10 20 30 40 50 clock frequency ? mhz added driver cycle-to-cycle jitter ? ps v cc = 3.3 v t a = 25c input = clock 20 28 36 44 52 60 20 40 60 80 100 signaling rate ? mbps added driver peak-to-peak jitter ? ps v cc = 3.3 v t a = 25c 2 15 -1 prbs nrz
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 8 parameter measurement information figure 13. driver voltage and current definitions a. all resistors are 1% tolerance. figure 14. differential output voltage test circuit a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2 and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 and r2 are metal film, surface mount, 1%, and located within 2 cm of the d.u.t. d. the measurement of v os(pp) is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 15. test circuit and definitions for the driver common-mode output voltage figure 16. driver short-circuit test circuit 10 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a v os r124.9 a/y c32.5 pf v os(pp) v os(ss) v os(ss) 1.3 v b/z a/y 0.7 v b/z d r224.9 c11 pf c2 1 pf v ab or v yz 49.9 w 3.32 k w 3.32 k w _ + -1 v v test 3.4 v a/yb/z d v ab or v yz a/y b/z i a or i y v b or v z v a or v y v os v a + v b 2 v i d v cc v y + v z 2 or i b or i z i i v test + - a/yb/z i os 0 v or v cc -1 v or 3.4 v
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 parameter measurement information (continued) a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2, and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 17. driver test circuit, timing, and voltage definitions for the differential output signal a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2, c3, and c4 includes instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 and r2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 18. driver enable and disable time circuit and definitions copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a a/yb/z r1 24.9 w t pzh t phz t pzl t plz v cc v cc /2 0 v~ 0.6 v 0.1 v0 v ~ -0.6 v 0 v-0.1 v de output with d at v cc output 0 v or v cc de output with d at 0 v c11 pf r2 24.9 w c40.5 pf c21 pf d c32.5 pf output a/y output t plh t phl input c30.5 pf b/z d 0 v 0.9v v 0 v t f t r v cc v cc /2 0 v ss ss 0 v 0.1v ss ss c11 pf c2 1 pf v p(h) v p(l) r150 w
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com parameter measurement information (continued) figure 19. maximum steady state output voltage a. all input pulses are supplied by an agilent 81250 stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 50 mhz 50 1% duty cycle clock input. d. peak-to-peak jitter is measured using a 100 mbps 2 15 ? 1 prbs input. figure 20. driver jitter measurement waveforms figure 21. receiver voltage and current definitions 12 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a (v a + v b )/2 i o r v cm v o v id v a i a ab i b v b t c(n) 1/f0 0 v0 v period jitter 0 v diff peak to peak jitter 1/f0 prbs input output v a -v b or v y -v z v a -v b or v y -v z clock input ideal outputactual output v cc v cc /2 t jit(per) = t c(n) -1/f0 t jit(pp) 0 v v cc v cc /2 0 v v a -v b or v y -v z v a -v b or v y -v z a/yb/z 0 v or v cc 1.62 k w , 1% v a , v b , v y or v z
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 table 1. type-1 receiver input threshold test voltages resulting differential resulting common- applied voltages receiver input voltage mode input voltage (1) output v ia v ib v id v ic 2.400 0.000 2.400 1.200 h 0.000 2.400 ? 2.400 1.200 l 3.425 3.335 0.050 3.4 h 3.375 3.425 ? 0.050 3.4 l ? 0.975 ? 1.025 0.050 ? 1 h ? 1.025 ? 0.975 ? 0.050 ? 1 l (1) h= high level, l = low level, output state assumes receiver is enabled ( re = l) table 2. type-2 receiver input threshold test voltages resulting differential resulting common- applied voltages receiver input voltage mode input voltage output (1) v ia v ib v id v ic 2.400 0.000 2.400 1.200 h 0.000 2.400 ? 2.400 1.200 l 3.475 3.325 0.150 3.4 h 3.425 3.375 0.050 3.4 l ? 0.925 ? 1.075 0.150 ? 1 h ? 0.975 ? 1.025 0.050 ? 1 l (1) h= high level, l = low level, output state assumes receiver is enabled ( re = l) a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. c l is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the d.u.t. b. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 22. receiver timing test circuit and waveforms copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 1.2 v1.0 v t plh 0.2 v -0.2 v v a v b v id 90% v oh v ol t phl 10% t f t r v o v cc /2 v o v id v b v a c l 0 v 15 pf
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. r l is 1% tolerance, metal film, surface mount, and located within 2 cm of the d.u.t. c. c l is the instrumentation and fixture capacitance within 2 cm of the dut and 20%. figure 23. receiver enable and disable time test circuit and waveforms 14 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 15 pf t pzl t plz v ol v ol +0.5 v v o r l 499 w _ + v test ba re 1.2 v inputs v cc 1 vv cc v cc /2 0 vv cc v cc /2 v test a re r 0 v 1.4 v a t pzh t phz 0 v v oh -0.5 v v cc v cc /2 0 vv oh v cc /2 re v o r output v test c l
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 a. all input pulses are supplied by an agilent 8304a stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 50 mhz 50 1% duty cycle clock input. d. peak-to-peak jitter is measured using a 100 mbps 2 15 ? 1 prbs input. figure 24. receiver jitter measurement waveforms copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a t c(n) 1/f0 period jitter peak to peak jitter 1/f0 prbs input output clock input ideal output actualoutput t jit(per) = t c(n) -1/f0 t jit(pp) v a -v b inputs v a -v b 0.2 v - t ype 1 0.4 v - t ype 2 v ic 1 v v oh v cc /2 v ol v oh v ol v cc /2 v oh v ol v cc /2 v a v b
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 9 detailed description 9.1 overview the sn65mlvd20xa family of devices are multipoint-low-voltage differential (m-lvds) line drivers and receivers that are optimized to operate at signaling rates up to 100 mbps. all parts comply with the multipoint low-voltage differential signaling (m-lvds) standard tia/eia-899. these circuits are similar to their tia/eia-644 standard compliant lvds counterparts with added features to address multipoint applications. the driver output has been designed to support multipoint buses presenting loads as low as 30 and incorporates controlled transition times to allow for stubs off of the backbone transmission line. these devices have type-1 and type-2 receivers that detect the bus state with as little as 50 mv (for type-1) or 150 mv (for type-2) of differential input voltage over a common-mode voltage range of ? 1 v to 3.4 v. the type- 1 receivers exhibit 25 mv of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. type-2 receivers include an offset threshold to provide a known output state under open-circuit and bus-idle fault conditions. 9.2 functional block diagram figure 25. logic diagrams (positive logic) 9.3 feature description 9.3.1 power-on reset this family of devices operates and meets all the specified performance requirements for supply voltages in the range of 3 v to 3.6 v. when the supply voltage drops below 1.5 v (or is turning on and has not yet reached 1.5 v), power-on reset circuitry sets the driver output to a high-impedance state. 9.3.2 esd protection the bus terminals of the sn65mlvd20xa devices possess on-chip esd protection against 8-kv human body model (hbm) and 8 kv. 16 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 4 31 2 de d re r 67 ab 54 2 3 de d re r 12 11 ab 10 9 yz sn65mlvd202a, sn65mlvd205a sn65mlvd200a, sn65mlvd204a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 9.4 device functional modes 9.4.1 device function tables table 3. type-1 receiver (sn65mlvd200a) (1) inputs output v id = v a - v b re r v id 50 mv l h ? 50 mv < v id < 50 mv l ? v id ? 50 mv l l x h z x open z (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? = indeterminate table 4. type-2 receiver (sn65mlvd204a) (1) inputs output v id = v a - v b re r v id 150 mv l h 50 mv < v id < 150 mv l ? v id 50 mv l l x h z x open z (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? = indeterminate table 5. driver (1) inputs enable outputs d de a b l h l h h h h l open h l h x open z z x l z z (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? = indeterminate copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 9.4.2 equivalent input and output schematic diagrams 18 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 360 k w 400 w v cc driver input and driver enable d or de 7 v 400 w v cc re 7 v receiver enable v cc 7 v 10 w 10 w receiver output 360 k w driver output a/y or b/z r v cc 200 k w 250 k w 200 k w 250 k w 100 k w 100 k w v cc receiver input b a
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the sn65mlvd20xa family of devices are multipoint line drivers and receivers. the functionality of these devices is simple, yet extremely flexible, thus leading to their use in designs ranging from wireless base stations to desktop computers. 10.2 typical application figure 26 shows a multipoint configuration. in a multipoint configuration, many transmitters and many receivers can be interconnected on one transmission line. the key difference compared to multidrop is the presence of two or more drivers. such a situation creates contention issues that must not be addressed with point-to-point or multidrop systems. multipoint operation allows for bidirectional, half-duplex communication over one balanced media pair. to support the location of the various drivers throughout the transmission line, double termination of the transmission line is now necessary. the major challenge that system designers encounter are the impedance discontinuities that device loading and device connections (stubs) introduce on the common bus. matching the impedance of the loaded bus and using signal drivers with controlled signal edges are the keys to error-free signal transmissions in multipoint topologies. figure 26. multipoint configuration 10.2.1 design requirements for this design example, use the parameters listed in table 6 . table 6. design parameters parameters values driver supply voltage 3 v to 3.6 v driver input voltage 0.8 v to 3.3 v driver signaling rate dc to 100 mbps interconnect characteristic impedance 100 (differential) termination resistance 100 number of receiver nodes 2 to 32 receiver supply voltage 3 v to 3.6 v receiver input voltage 0 to (v cc ? 0.8) v receiver signaling rate dc to 100 mbps ground shift between driver and 1 v receiver copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a r d r d r d r d ~ 100 ~ ~ 100 ~
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 10.2.2 detailed design procedure 10.2.2.1 supply voltage the sn65mlvd20xa devices are operated from one supply. the sn65mlvd20xa devices can support operation with a supply as low as 3 v and as high as 3.6 v. 10.2.2.2 supply bypass capacitance bypass capacitors play a key role in power distribution circuitry. at low frequencies, power supply offers very low- impedance paths between its terminals. however, as higher frequency currents propagate through power traces, the source is often incapable of maintaining a low-impedance path to ground. bypass capacitors are used to address this shortcoming. usually, large bypass capacitors (10 f to 1000 f) at the board level do a good job up into the khz range. due to their size and length of their leads, large capacitors tend to have large inductance values at the switching frequencies. to solve this problem, smaller capacitors (in the nf to f range) must be installed locally next to the integrated circuit. multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nh. for comparison purposes, a typical capacitor with leads has a lead inductance around 5 nh. the value of the bypass capacitors used locally with m-lvds chips can be determined by equation 1 and equation 2 , according to high speed digital design ? a handbook of black magic by howard johnson and martin graham (1993). a conservative rise time of 4 ns and a worst-case change in supply current of 100 ma covers the whole range of m-lvds devices offered by texas instruments. in this example, the maximum power supply noise tolerated is 100 mv; however, this figure varies depending on the noise budget available for the design. (1) (2) figure 27 shows a configuration that lowers lead inductance and covers intermediate frequencies between the board-level capacitor ( > 10 f) and the value of capacitance found above (0.004 f). place the smallest value of capacitance as close as possible to the chip. figure 27. recommended m-lvds bypass capacitor layout 10.2.2.3 driver input voltage the input stage accepts lvttl signals. the driver will operate with a decision threshold of approximately 1.4 v. 10.2.2.4 driver output voltage the driver outputs a steady state common mode voltage of 1 v with a differential signal of 540 v under nominal conditions. 20 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 0.1 f 0.004 f 3.3 v mlvds 100 ma c 4ns 0.004 f 100 mv ? ? = = m ? ? maximum step change supply current chip rise time maximum power supply noise i c t v ? ? d = ? ? d ?
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 10.2.2.5 termination resistors an m-lvds communication channel employs a current source driving a transmission line that is terminated with two resistive loads. these loads serve to convert the transmitted current into a voltage at the receiver input. to ensure good signal integrity, the termination resistors must be matched to the characteristic impedance of the transmission line. the designer must ensure that the termination resistors are within 10% of the nominal media characteristic impedance. if the transmission line is targeted for 100- impedance, the termination resistors must be between 90 and 110 . the line termination resistors are typically placed at the ends of the transmission line. 10.2.2.6 receiver input signal the m-lvds receivers herein comply with the m-lvds standard and correctly determine the bus state. these devices have type-1 and type-2 receivers that detect the bus state with as little as 50 mv of differential voltage over the common mode range of ? 1 v to 3.4 v. 10.2.2.7 receiver input threshold (failsafe) the m-lvds standard defines a type-1 and a type-2 receiver. type-1 receivers have differential input voltage thresholds near zero volts. type-2 receivers have differential input voltage thresholds offset from 0 v to detect the absence of a voltage difference. the impact to receiver output by the offset input can be seen in table 7 and figure 28 . table 7. receiver input voltage threshold requirements receiver type output low output high type 1 ? 2.4 v v id ? 0.05 v 0.05 v v id 2.4 v type 2 ? 2.4 v v id 0.05 v 0.15 v v id 2.4 v figure 28. expanded graph of receiver differential input voltage showing transition region 10.2.2.8 receiver output signal receiver outputs comply with lvttl output voltage standards when the supply voltage is within the range of 3 v to 3.6 v. 10.2.2.9 interconnecting media the physical communication channel between the driver and the receiver may be any balanced, paired metal conductors that meet the requirements of the m-lvds standard ? the key points are included in the following. the interconnecting media may be a twisted pair, twinax, flat ribbon cable, or pcb traces. the nominal characteristic impedance of the interconnect must be between 100 and 120 with variation no more than 10% (90 to 132 ). copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a -100 -50 0 50 100 150 200 t ype 1 t ransition regions t ype 2 low high low high differential input voltage (mv)
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com 10.2.2.10 pcb transmission lines the lvds owner's manual design guide, 4th edition ( snla187 ), figure 29 depicts several transmission line structures commonly used in printed-circuit boards (pcbs). each structure consists of a signal line and a return path with uniform cross-section along its length. a microstrip is a signal trace on the top (or bottom) layer that is separated by a dielectric layer from its return path in a ground or power plane. a stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. the dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line, which is also called controlled-impedance transmission line . when two signal lines are placed close together, they form a pair of coupled transmission lines. figure 29 shows examples of edge-coupled microstrips and edge-coupled or broad-side-coupled striplines. when excited by differential signals, the coupled transmission line is referred to as a differential pair. the characteristic impedance of each line is called odd-mode impedance . the sum of the odd-mode impedances of each line is the differential impedance of the differential pair. in addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. when the two lines are immediately adjacent (for example, if s is less than 2 w) the differential pair is called a tightly- coupled differential pair. to maintain constant differential impedance along the length, it is important to keep the trace width and spacing uniform along the length and to maintain good symmetry between the two lines. figure 29. controlled-impedance transmission lines 22 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a 0 r 87 5.98 h z ln 0.8 w t 1.41 ? h ? 1 > @ > @ 0 r 1.9 2 h t 60 z ln 0.8 w t ? ? h ? 1 s 0.96 h diff 0 z 2 z 1 0.48 e u ? u u u ? ? 1 s 2.9 h diff 0 z 2 z 1 0.347 e u ? u u u ? ? 1 co-planar coupled microstrips broad-side coupled striplines edge-coupled edge-coupled single-ended microstrip single-ended stripline w h t w t h h s h differential microstrip differential stripline s h s h h g g w w w s
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 10.2.3 application curves 100 mbps 2 15 ? 1 prbs c l = 15 pf 100 mbps 2 15 ? 1 prbs r l = 50 ? figure 31. sn65mlvd200a receiver output eye pattern figure 30. sn65mlvd200a driver output eye pattern 11 power supply recommendations the m-lvds drivers and receivers in this data sheet are designed to operate from one power supply. both drivers and receivers operate with supply voltages in the range of 3 v to 3.6 v. in a typical application, a driver and a receiver may be on separate boards or even separate equipment. in these cases, separate supplies must be used at each location. the expected ground potential difference between the driver power supply and the receiver power supply would be less than 1 v. board level and local device level bypass capacitance must be used and are covered supply bypass capacitance. 12 layout 12.1 layout guidelines 12.1.1 microstrip versus stripline topologies according to the lvds application and data handbook ( slld009 ), printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. microstrips are traces on the outer layer of a pcb, as shown in figure 32 . figure 32. microstrip topology copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a horizontal scale = 2 ns/div vertical scale = 127.2 mv/div horizontal scale = 2 ns/div vertical scale = 400 mv/div
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com layout guidelines (continued) striplines are traces between two ground planes (see figure 33 ). striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. however, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. ti recommends routing m-lvds signals on microstrip transmission lines if possible. the pcb traces allow designers to specify the necessary tolerances for z o based on the overall noise budget and reflection allowances. footnotes 1 (1) , 2 (2) , and 3 (3) provide the documentation for formulas for z o and t pd for differential and single-ended traces. (1) (2) (3) figure 33. stripline topology 12.1.2 dielectric type and board construction the speeds at which signals travel across the board dictates the choice of dielectric. fr-4, or equivalent, usually provides adequate performance for use with m-lvds signals. if rise or fall times of ttl/cmos signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as rogers ? 4350 or nelco n4000-13 is better suited. when the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. the following set of guidelines were developed experimentally through several designs involving m-lvds devices: ? copper weight: 15 g or ? oz start, plated to 30 g or 1 oz ? all exposed circuitry must be solder-plated (60/40) to 7.62 m or 0.0003 in (minimum) ? copper plating must be 25.4 m or 0.001 in (minimum) in plated-through-holes ? solder mask over bare copper with solder hot-air leveling 12.1.3 recommended stack layout following the choice of dielectrics and design specifications, the designer must decide how many levels to use in the stack. to reduce the ttl/cmos to m-lvds crosstalk, it is a good practice to have at least two separate signal planes as shown in figure 34 . figure 34. four-layer pcb board note the separation between layers 2 and 3 must be 127 m (0.005 in). by keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. (1) howard johnson and martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. (2) mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. (3) clyde f. coombs. 1995. printed circuits handbook. mcgraw hill. isbn number 0070127549. 24 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a layer 4: routed plane (ttl/cmos signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (mlvds signals)
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 layout guidelines (continued) one of the most common stack configurations is the six-layer board, as shown in figure 35 . figure 35. six-layer pcb board in this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. the result is improved signal integrity; however, fabrication is more expensive. using the 6-layer board is preferable because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 12.1.4 separation between traces the separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. low-noise coupling requires close coupling between the differential pair of an m-lvds link to benefit from the electromagnetic field cancellation. the traces must be 100- ? differential and coupled in the manner that best fits this requirement. in addition, differential pairs must have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. in the case of two adjacent single-ended traces, one must use the 3-w rule, which stipulates that the distance between two traces must be greater than two times the width of one trace, or three times its width measured from trace center to trace center. this increased separation effectively reduces the potential for crosstalk. the same rule must be applied to the separation between adjacent m-lvds differential pairs, whether the traces are edge-coupled or broad-side-coupled. figure 36. 3-w rule for single-ended and differential traces (top view) exercise caution when using autorouters because they do not always account for all factors affecting crosstalk and signal reflection. for instance, it is best to avoid sharp 90 turns to prevent discontinuities in the signal path. using successive 45 turns tends to minimize reflections. 12.1.5 crosstalk and ground bounce minimization to reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. a ground plane usually achieves this. because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. lowering the area of the current loop lowers the potential for crosstalk. traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. discontinuities in the ground plane increase the return path inductance and must be avoided. copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a layer 4: routed plane (ttl signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (mlvds signals) layer 4: ground plane layer 5: ground plane t 2 w w ww minimum spacing as defined by pcb vendor mlvds pair ttl/cmos trace differential traces single-ended traces s =
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com layout guidelines (continued) 12.1.6 decoupling each power or ground lead of a high-speed device must be connected to the pcb through a low inductance path. for best results, one or more vias are used to connect a power or ground pin to the nearby plane. ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. placing a power plane closer to the top of the board reduces the effective via length and its associated inductance. figure 37. low inductance, high-capacitance power connection bypass capacitors must be placed close to v dd pins and can be placed conveniently near the corners or underneath the package to minimize the loop area. this extends the useful frequency range of the added capacitance. small physical-size capacitors (such as 0402, 0201, or x7r surface-mount capacitors) must be used to minimize body inductance of capacitors. each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in figure 38 (a). an x7r surface-mount capacitor of size 0402 has about 0.5 nh of body inductance. at frequencies above about 30 mhz, x7r capacitors behave as low-impedance inductors. to extend the operating frequency range to a few hundred mhz, an array of different capacitor values like 100 pf, 1 nf, 0.03 f, and 0.1 f are commonly used in parallel. the most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. with a 2-mil fr4 dielectric, there is approximately 500 pf per square inch of pcb. many high-speed devices provide a low-inductance gnd connection on the backside of the package. this center pad must be connected to a ground plane through an array of vias. the via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (smt) package. placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest possible die temperature. placing high-performance devices on opposing sides of the pcb using two gnd planes (as shown in figure 29 ) creates multiple paths for heat transfer. thermal pcb issues are often the result of one device adding heat to another, resulting in a very high local temperature. multiple paths for heat transfer minimize this possibility. in many cases, the gnd pad that is so important for heat dissipation makes the optimal decoupling layout impossible to achieve, due to insufficient pad- to-pad spacing as shown in figure 39 (b). when this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum. 26 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a board thickness approximately 100 mil 2 mil typical 12-layer pcb 4 mil 4 mil 6 mil 6 mil v cc via gnd via top signal layer + gnd fill v dd 1 plane gnd plane signal layer buried capacitor > signal layer gnd plane v dd 2 plane bottom signal layer + gnd fill buried capacitor > gnd plane signal layers v cc plane
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 layout guidelines (continued) it is important to place the v dd via as close to the device pin as possible while still allowing for sufficient solder mask coverage. if the via is left open, solder may flow from the pad into the via barrel, which results in a poor solder connection figure 38. typical decoupling capacitor layout (a) figure 39. typical decoupling capacitor layout (b) 12.2 layout example at least two or three times the width of an individual trace must separate single-ended traces and differential pairs to minimize the potential for crosstalk. single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. increase the spacing between signal paths for long parallel runs to reduce crosstalk. boards with limited real estate can benefit from the staggered trace layout, as shown in figure 40 . figure 40. staggered trace layout this configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. to ensure continuity in the ground signal path, ti recommends having an adjacent ground via for every signal via, as shown in figure 41 . note vias create additional capacitance. for example, a typical via has a lumped capacitance effect of ? pf to 1 pf in fr4. copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a layer 6 layer 1 0402 v dd in in+ 0402
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a slls573d ? december 2003 ? revised december 2015 www.ti.com layout example (continued) figure 41. ground via location (side view) short and low-impedance connection of the device ground pins to the pcb ground plane reduces ground bounce. holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. to minimize emi problems, ti recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. 13 device and documentation support 13.1 documentation support 13.1.1 related documentation for related documentation, see the following: ? introduction to m-lvds (tia/eia-899) ( slla108 ) ? lvds application and data handbook ( slld009 ) ? lvds owner's manual design guide, 4th edition ( snla187 ) ? semiconductor and ic package thermal metrics ( spra953 ) ? howard johnson and martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. ? mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. ? clyde f. coombs. 1995. printed circuits handbook. mcgraw hill. isbn number 0070127549. 13.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8. related links technical tools & support & parts product folder sample & buy documents software community sn65mlvd200a click here click here click here click here click here sn65mlvd202a click here click here click here click here click here sn65mlvd204a click here click here click here click here click here sn65mlvd205a click here click here click here click here click here 28 submit documentation feedback copyright ? 2003 ? 2015, texas instruments incorporated product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a signal trace uninterrupted ground plane signal trace uninterrupted ground plane signal via ground via
sn65mlvd200a , sn65mlvd202a sn65mlvd204a , sn65mlvd205a www.ti.com slls573d ? december 2003 ? revised december 2015 13.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.4 trademarks e2e is a trademark of texas instruments. rogers is a trademark of rogers corporation. all other trademarks are the property of their respective owners. 13.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 13.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2003 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: sn65mlvd200a sn65mlvd202a sn65mlvd204a sn65mlvd205a
package option addendum www.ti.com 28-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn65mlvd200ad active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf200a sn65mlvd200adg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf200a sn65mlvd200adr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf200a sn65mlvd200adrg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf200a sn65mlvd202ad active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd202a sn65mlvd202adg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd202a SN65MLVD202ADR active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd202a sn65mlvd204ad active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf204a sn65mlvd204adg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf204a sn65mlvd204adr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf204a sn65mlvd204adrg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf204a sn65mlvd205ad active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd205a sn65mlvd205adg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd205a sn65mlvd205adr active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mlvd205a (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 28-oct-2015 addendum-page 2 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn65mlvd200adr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 SN65MLVD202ADR soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 sn65mlvd204adr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 sn65mlvd205adr soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 package materials information www.ti.com 28-oct-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn65mlvd200adr soic d 8 2500 340.5 338.1 20.6 SN65MLVD202ADR soic d 14 2500 333.2 345.9 28.6 sn65mlvd204adr soic d 8 2500 340.5 338.1 20.6 sn65mlvd205adr soic d 14 2500 333.2 345.9 28.6 package materials information www.ti.com 28-oct-2015 pack materials-page 2

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